March Test for Static Neighborhood Pattern-Sensitive Faults in Random-Access Memories

Low Power March Memory Test Algorithm for Static Random Access Memories (TECHNICAL NOTE)

Memories are most important building blocks in many digital systems. As the Integrated Circuits requirements are growing, the test circuitry must grow as well. There is a need for more efficient test techniques with low power and high speed. Many Memory Built in Self-Test techniques have been proposed to test memories. Compared with combinational and sequential circuits memory testing utilizes ...

March Test for Static 3-Coupling Faults in Random-Access Memories

− A march test of length 30n for detecting static 3-coupling faults in n × 1 random-access memories (RAMs) is presented. To reduce the length of the test, only the coupling faults between physically adjacent memory cells have been considered. The test assumes that the storage cells are arranged in a rectangular grid and that the mapping from logical addresses to physical cell locations is known...

A Fault Coverage Evaluation of Linked Neighborhood Pattern-Sensitive Faults in Random-Access Memories

A fault coverage evaluation concerning a linked neighborhood pattern sensitive faults model (NPSFs) in N × 1 random-access memories is presented. For the simulation study, the most important published tests dedicated to the NPSF model have been considered. Simulation results show that these tests cover the entire model of simple NPSFs, but only the longer of them cover the linked NPSF model. In...

Testing Static and Dynamic Faults in Random Access Memories

The ever increasing trend to reduce DPM levels of memories requires tests with very high fault coverages. The very important class of dynamic fault, therefore cannot be ignored any more. It will be shown in this paper that conventional memory tests constructed to detect the static faulty behavior of a specific defect do not necessarily detect its dynamic faulty behavior; which has been shown to...

Parallel Testing for Pattern-Sensitive Faults in Semiconductor Random-Access Memories